With a popularization of various types of personal mobile products, an application processor (AP) for use in the mobile products has been advanced to a level of a personal computer (PC) processor that is superior in performance and supports more functionalities. For battery-constrained mobile devices, however, battery power conservation is one of the most critical issues. In order to fulfill both higher performance and lower power requirements, a variety of techniques is applied to the AP.
Analyzing battery power usage pattern of a smartphone, about 60% of total battery power is consumed in a standby mode. Alternatively, the battery power consumption in the standby mode is larger than the user expected because various services (such as health/motion sensing services, recognition services, location services) including a basic telephony function are running in the standby mode. In order to support such services, a central processing unit (CPU) in the AP performs simple operations with external data generating periodically. Since the CPU of the AP and a main storage device (such as DRAM) basically consume higher power an AP chip needs to include various modules like hardware modules and auxiliary processing units such as a digital signal processor (DSP) capable of performing simple operations with the external data generating periodically as well as the CPU. Therefore, an efficient controlling technique for cache memory of the AP chip is needed while proving a higher performance and a lower power consumption.